求高手修改一下关于EDA的毕业设计
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY basifre_product IS
PORT ( clk_1kh : IN std_logic;
fre_100h,fre_10h,fre_1h : OUT std_logic);
END basifre_product;
ARCHITECTURE stru OF basifre_product IS
COMPONENT cont10
PORT( clk,rst,en : IN std_logic;
count : OUT integer RANGE 0 TO 9 ;
ca_rry : OUT std_logic);
END COMPONENT ;
SIGNAL vcc,gnd : std_logic;
SIGNAL fre_100h_t,fre_10h_t : std_logic;
BEGIN
vcc gnd ,en => vcc ,ca_rry => fre_100h_t ) ;
u2 : cont10 PORT MAP ( clk => fre_100h_t ,rst => gnd ,en => vcc ,ca_rry => fre_10h_t ) ;
u3 : cont10 PORT MAP ( clk => fre_10h_t ,rst => gnd ,en => vcc ,ca_rry => fre_1h ) ;
fre_100h basi_fre);
END beha_basifre ;
--follow is single impluse productor,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t IS
PORT (cp,cd : IN std_logic;
q : OUT std_logic);
END t;
ARCHITECTURE beha OF t IS
SIGNAL qq : std_logic;
BEGIN
PROCESS (cp,cd)
BEGIN
IF cd = '1' THEN
qq DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R
CASE DATA IS
WHEN 0 => DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R DISPLAY_R
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